As integrated circuit geometries continue to decline, circuits become more susceptible to both hard errors and soft errors. Hard errors are introduced by contaminants that physically damage the circuitry. For example, a hard error may occur when a particle is lodged in the gate oxide of a dynamic random access memory (DRAM) cell during fabrication. Typically, hard errors require that the entire integrated circuit be discarded. On the other hand, soft errors are transient in nature. In a DRAM, a soft error is an error in memory content that can be corrected by a fresh writing to the DRAM.
In addition to the decline in integrated circuit geometries in order to increase circuit density, reductions in power supply voltages increase the susceptibility of circuits to soft errors. A DRAM cell is able to store a charge in a capacitor, with the charged capacitor representing a logic “one” and a discharged capacitor representing a logic “zero.” A lower supply voltage translates into a smaller capacitor charge, so there is a greater likelihood that the charge will be unintentionally depleted to a level at which it will be mistakenly read as logic “zero.”
Another factor that affects the susceptibility of a circuit to soft errors relates to the operation of the device in which the circuit resides. Some devices must retain data in internal memories for extended periods of time between actual uses. If the executable code is stored in volatile memory during the periods of inactivity, soft errors in the executable code will accumulate and be undetected until the next use. In a DRAM cell, charge leakage may be the result of bombardment by radiation, such as alpha particles. Alpha particle radiation is generated as a consequence of decay of trace radioactive elements in the packaging material of the integrated circuit chip. With extended periods of inactivity, the adverse effects of such decay are more likely to cause system failures when the corrupted executable code is finally run.
Two examples of devices which are often operated with extended periods of inactivity between peak periods of high use are printer controllers and handheld computing devices. FIG. 1 is an example of an application specific integrated circuit (ASIC) 10 that receives executable code from external non-volatile memory 12. The ASIC includes a processor 14 and embedded memory for handling instructions. The processor cooperates with the memory capability of ASIC for high speed access to compressed instructions that are originally stored in the external memory 12. The processor portion of the ASIC includes cache static random access memory (SRAM) 24 and a cache memory controller 22, while the embedded memory portion includes DRAM 26, SRAM 28, a second memory controller 30, and a bus 32.
In operation, the cache SRAM 24 operates as conventional on-chip cache. The cache memory controller 22 manages the use of the cache SRAM 24 to free and fill space for instructions that are likely to be requested (i.e., fetched) by the processor 14. The embedded SRAM 28 and DRAM 26 may be managed by the second memory controller 30 to handle larger blocks of information for possible use by the processor. A printer having the ASIC is able to format incoming data in a page description language (PDL) and execute the instructions of a PDL interpreter program from cache, while the PDL program as a whole is stored in off-chip memory 12, which is typically memory of a host computer, such as a desktop computer.
There are a wide number of variations of ASICs that may be used in a printer, but each such circuit is likely to be operated in conditions in which it is “idle” for long periods between uses. It is during these idle times that soft errors are most likely to occur in the storage of executable code and/or data. Techniques for reducing such occurrences are known. For example, there are integrated circuit packaging materials that contain low levels of impurities that decay to generate alpha particles. By reducing the number of alpha particles that are generated, the statistical probability of a soft error is reduced. However, the cost of the materials is significantly greater than the cost of conventionally used packaging material. Thus, this solution increases the cost of integrated circuit chips.
Circuitry may be added to the device to provide detection of soft errors while the code is being run. One known scheme is to incorporate parity detection circuitry for detecting single and/or multiple bit errors. However, there is significant circuitry overhead that is added in providing the parity bit or bits. The additional circuitry increases the cost of the device. Another approach is to provide error-correction circuitry (ECC). ECC may be used to detect and correct single and/or multiple bit errors. The concerns with this approach are that there is an even greater increase in circuitry overhead that adds to the cost and there is additional complexity that can result in decreased performance in the SRAM/DRAM data path. The memory controller logic may become more complicated with the handling of extra processing states that may be required by the “repair” feature of the ECC.
What is needed is a low cost method and device for providing recovery from memory errors, particularly soft memory errors in executable code stored in volatile memory.